This application claims benefit of priority under 35 U.S.C. xc2xa7 119 to Japanese Patent Application No. Hei 11-349388 (1999), filed on Dec. 8, 1999, the entire contents of which are incorporated by reference therein.
The present invention relates generally to an Electrically Erasable Programmable Read Only Memory (EEPROM). More specifically, the invention relates to an EEPROM wherein a series of rewriting operations including verify operations are automatically sequentially controlled by a control circuit included in the EEPROM.
In recent typical EEPROM flash memories, a control circuit for sequentially controlling writing/erasing operations is provided in a chip. In an EEPROM of this type, if a command and writing data are inputted from the outside, a series of operations including a data writing operation and the subsequent verify operation are automatically carried out until a predetermined writing is completed. Until the writing is completed after the writing operation is started, a busy signal is outputted to the outside to inhibit access.
Such a waiting time in the busy state of the EEPROM flash memory adversely affects the high-speed performance of a memory system. Therefore, in order to realize a high-speed performance in a flash memory system using a plurality of memory chips, it is effective to commonly use a data bus for time-sharing inputting commands and data to carry out internal operations in the plurality of memory chips in parallel. The inventors have proposed such a technique (Japanese Publication (Kokai) Nos. 07-302175 and 07-302176, U.S. Pat. No. 5,603,001, etc.).
However, in recent years, the storage capacity of a single chip of flash memories increases more and more. Assuming that a single chip is enough for the storage capacity of a required memory system, the above described time-sharing control technique using the plurality of chips can not be applied, so that the high-speed performance can not be obtained. Therefore, it is desired to provide a single chip capable of realizing a high-speed performance by the same time-sharing control and parallel processing as those when the above described plurality of chips are used.
As circumstances on the side of a Central Processing Unit (CPU) for controlling a memory system, there are also circumstances wherein even if the storage capacity of a required memory system increases, the size of a handled file other than image files often does not remarkably increase, and many small-size files are rather preferably handled. The page mapping size of the CPU of personal computers is also maintained to be, e.g., 4 kilobytes, as a common value regardless of the generation of the CPU.
In view of such a host system environment, it is not always adequate to increase the writing page size and erasing block size of a memory device in accordance with the increase of the storage capacity of the memory device, and even if the storage capacity increases, there are often cases where writing and erasing can be preferably carried out every small capacity unit.
It is therefore an object of the present invention to eliminate the aforementioned problems and to provide a nonvolatile semiconductor memory device capable of controlling a single memory chip similar to a plurality of memory chips.
In order to accomplish the aforementioned and other objects, according to one aspect of the present invention, there is provided an electrically rewritable nonvolatile semiconductor memory device comprising: a plurality of memory circuits, each of which has a control circuit for sequentially controlling writing, provided in a memory chip so as to share a data bus, and a chip enable terminal for controlling the activity and inactivity of each of the memory circuits provided for each of the memory circuits.
According to another aspect of the present invention, there is provided an electrically rewritable nonvolatile semiconductor memory device having a plurality of memory circuits, each of which has a control circuit for sequentially controlling writing, provided in a memory chip so as to share a data bus, wherein the activity and inactivity of each of the memory circuits are controlled by inputting a command.
According to a further aspect of the present invention, there is provided an electrically rewritable nonvolatile semiconductor memory device having a plurality of memory circuits, each of which has a control circuit for sequentially controlling writing, provided in a memory chip so as to share a data bus, wherein the activity and inactivity of each of the memory circuits are controlled by inputting a command.
According to the present invention, a plurality of memory circuits (EEPROM circuits) in a single chip can be operated in time sharing or in parallel as if plural chips are operated. Therefore, unlike a case where the storage capacity of a single chip is simply increased by a single control circuit, even if a certain circuit is in a busy state, it is possible to access other memory circuits, so that it is possible to obtain a high-speed performance memory system without waiting time at sight from the outside.